CacheQ exposes GPU support for the QCC development environment

LOS GATOS, CALIF., – CacheQ Systems, Inc. announced GPU support for its QCC Acceleration Platform. It is a heterogeneous computing development environment that provides faster performance and lower development time for computer architectures including multi-core processors, GPUs, and programmable gate arrays (FPGA).

“The demand for hardware acceleration with GPUs and other heterogeneous computing hardware is growing exponentially,” notes Clay Johnson, CEO and co-founder of CacheQ Systems, a developer of heterogeneous acceleration solutions. Our goal is to simplify the high-performance data center and develop edge computing applications. The QCC accelerator platform achieves this goal and will enable new solutions across a variety of applications.

GPU deployment has progressed at a rapid pace in the past five years. The $25 billion annually industry is expected to continue to grow at a compound annual growth rate of approximately 33% through 2028.

The advantage of the QCC accelerator platform

Heterogeneous computing systems such as multi-core processors and GPUs as well as the FPGAS associated with these processing systems have relied on software tools supported by hardware vendors and the open source community. These tools have traditionally relied on software developers to pass information to compilers. This is to express parallelism in their code through hardware APIs such as CUDA from NVIDIA, HIP from AMD, and oneAPI from Intel.

Other efforts attempt to support built-in pragmas in C, C++, and Fortran through OpenACC, OpenMP, and OpenCL. They all require deep knowledge of the target hardware to control memory copying and synchronization events. In addition, to create teams from threads, manually remove the loop load dependencies, race conditions, and add abstracts. The purpose is to achieve performance and correct code behavior on parallel compute units.

CacheQ QCC is the first compiler platform to automatically extract parallelism from standard C, C++, and Fortran code. It does not require the developer to explicitly communicate parallelism to the compiler. AQCC automatically accelerates applications using a variety of devices, outperforming pragma-based methods. It can also handle manually coded API solutions with minimal hardware knowledge. This allows the developer to write generic code and target high-performance hardware at compile time without refactoring, or refactoring in a way that does not target specific hardware and is easily functionally verifiable.

Based on the CacheQ Virtual Machine (CQVM), the QCC Acceleration Platform is a heterogeneous computing development environment that converts high-level serial language (HLL) code into a parallel representation in less than 30 seconds for the most complex designs. It supports code profiling, usage estimations, performance simulation, and memory configuration and segmentation across a variety of compute engine processors including GPUs, x86, Arm, RISC-V, and FPGAs before computationally generating an executable.

Features:

Features include a development environment with unified drivers, protected containers, and support for multiple boards from multiple vendors. Its design analysis offers profiling, performance simulation, and memory activity reports. The optimization capability adds user-driven decoding, memory configuration, and automatic, user-directed partitioning.

An FPGA implementation includes a resource estimator, pre-made wrappers, multiple boards and parts, and implementation tool automation. The memory implementation supports automatic integration, multi-port/multi-access and stripe.

Availability and pricing

The QCC acceleration platform ships now in limited quantities with general availability in the project in late 2023. Version 0.18 supports GPUs from nVidia and AMD acceleration boards, Xilinx FPGAs and CPUs from Intel, AMD, Arm, Apple and RISC-V.

Pricing is available upon request.

In the meantime, visit the CacheQ site for additional information, demo requests or early access to the QCC accelerator platform.

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